1. Field of the Invention
The present invention relates to an information processing system and a control method thereof, and more particularly to an information processing system including a semiconductor device with a self-refresh mode and a control method thereof. The present invention also relates to a control method of a controller, and more particularly to a controller that controls a semiconductor device with a self-refresh mode and a control method thereof.
2. Description of Related Art
In a semiconductor device that performs an operation in synchronism with a clock signal such as asynchronous DRAM (Dynamic Random Access Memory), an internal clock signal phase-controlled is often required inside of the semiconductor device. The phase-controlled internal clock signal is mainly generated by a DLL (Delay Locked Loop) circuit included in the semiconductor device (see Japanese Patent Application Laid-open No. 2011-61457). The DLL circuit includes a delay line that delays the internal clock signal and a delay amount thereof is determined based on a count value output from a counter circuit. The counter circuit is controlled by a phase control circuit having a comparing unit that compares phases of an external clock signal supplied from outside and the internal clock signal. Because the DLL circuit is a circuit block that consumes a relatively large amount of power, the semiconductor device described in Japanese Patent Application Laid-open No. 2011-61457 reduces power consumption by intermittently performing a phase control operation.
Meanwhile, an operation mode called a self-refresh mode is provided for the DRAM. The self-refresh mode is a kind of standby mode in which refresh of storage data included in storage cells is periodically performed inside of the DRAM asynchronously with outside. A controller can stop issuance of many external signals such as an external clock signal and a command signal to be supplied to the semiconductor device, during a period when the semiconductor device has entered the self-refresh mode. During the period when the semiconductor device has entered the self-refresh mode, an input first-stage circuit such as a clock receiver included in the DRAM to receive a signal supplied from outside is inactivated and operations of circuit blocks such as the DLL circuit are also stopped. Accordingly, when the semiconductor device has entered the self-refresh mode, entire power consumption of the system becomes quite low. Furthermore, the refresh operation is periodically performed inside of the DRAM, so that the storage data are not lost.
However, because the operation of the DLL circuit stops during the period when the semiconductor device has entered the self-refresh mode, it takes a long time for the DLL circuit to be locked again (for example, to set a delay amount reset in the DLL circuit to match phases of the external clock signal and the internal clock signal with each other) after the semiconductor device exits the self-refresh mode. This means delay of a command issued by the controller after the exit. This means, for example, that a long time is required after the semiconductor device exits the self-refresh mode and before input of a command requiring a phase-controlled internal clock signal becomes possible.
To solve this problem, a method that enables to intermittently activates an DLL circuit also during a period when a semiconductor device has entered a self-refresh mode is proposed in Japanese Patent Application Laid-open No. 2001-332086. Although such an operation does not comply with DRAM standards, a time required after the semiconductor device exits from the self-refresh mode and before the DLL circuit is locked again can be greatly reduced by performing this operation.
However, in the DRAM described in Japanese Patent Application Laid-open No. 2001-332086, a clock receiver included in the DRAM needs to be activated in the same manner as in a normal mode other than the self-refresh mode to enable the operation of the DLL circuit even in the self-refresh mode. Accordingly, even when the semiconductor device has entered the self-refresh mode, power consumption of the clock receiver cannot be reduced. That is, the method according to Japanese Patent Application Laid-open No. 2001-332086 enables to reduce the lock time after the exit; however, low power consumption, which is superiority of the self-refresh, is sacrificed. Therefore, reduction in the lock time after the exit while maintaining merits of the self-refresh is demanded.
This problem occurs not only in the DRAM but also in all semiconductor devices with the self-refresh mode. For example, there is the same problem also in a semiconductor device that in a part includes nonvolatile memory cells having a problem of cell data retention.